Heretofore, in a memory device such as a main memory used for a computer system of a multi-CPU configuration, a plurality of memory modules (referred to also as memory bank) serving as memory elements independently accessible are mounted on a board, thereby constructing a memory device, and a memory module used for such memory device is unable to avoid a fluctuation of the quality caused by the production process of the memory module. Due to the fluctuation of the quality caused by the production of this memory module, there are often the cases where abnormality occurs in which normal reading and wiring are unable to be performed in a part of the address, while being mounted and used in the memory device. When the memory abnormality is detected, it is important that the memory module causing the memory abnormality is specified and the abnormal portion is eliminated from the system, thereby to stably operate the system. With respect to the memory module once recognized as abnormal, even if the memory configuration is changed by a change of the number of ways of interleave control, until the abnormal memory module is exchanged, it is required not to be incorporated into the system for the sake of the improvement of the robustness in the operational system, the malfunction maintenance work time when malfunction occurs after starting the operation, and saving in the cost for maintenance. Hence, in the conventional memory device, when the memory abnormality is detected by the hardware function of the memory controller, the memory module causing the memory abnormality is specified, and the abnormal part is eliminated from the system. That is, the memory controller divides the address space of the memory module seen from the CPU into the areas of an appropriate size, and when the abnormality of the memory module is detected, a memory control of degenerating a memory is performed such that the area corresponding to the abnormal portion is set as an utilization prohibition area, and the area including the abnormal portion are not incorporated into an utilizable area by the CPU.
Patent Document 1: JP-A-02-166543
Patent Document 2: JP-A-04-165548
However, in the conventional memory control, since the function degenerating so as to specify a memory module causing memory abnormality not to be incorporated into the system has been mounted by the hardware function, the increase in the cost and the size due to the increase of a mounted circuit has become a problem. Further, in the conventional memory control method for dividing the address space of the memory module visible from the CPU into the areas of an appropriate size and managing the areas utilizable by the CPU, no measures can be taken when the memory configuration is changed by the change of the number of ways in the interleave control.
For example, when the number of ways of the interleave control is changed from a 1-way (no interleave) to a 2-way memory configuration, a corresponding relationship between the real address of the memory module and a logic address visible from the CPU is also changed, and for example, while the address of the abnormal location before the change of the memory configuration corresponds to an m-th area, after the change of the memory configuration, a situation may develop where the address of the abnormal portion comes to correspond to another n-th area. Hence, the problem is that, after changing the memory configuration, the abnormal portion of the memory module is specified again, and with respect to the divided areas of the address space visible from the CPU after the change of the configuration, the area corresponding to the abnormal portion of the memory module is determined and set as an area for utilization prohibition, and area management for not incorporating the area including the abnormal portion into the utilizable area of the CPU is required, and area utilization information before the change of the configuration is unable to be taken over after the change of the configuration, and a process load for deciding the area utilizable by the CPU after the memory re-configuration is increased, and re-starting the process after the change of the memory configuration takes time.